1. Field of the Invention
The invention relates generally to a method of forming a floating gate in a flash memory device, and more particularly to, a method of forming a floating gate in a flash memory device capable of securing a space of the floating gate.
2. Description of the Prior Art
Generally, a method of manufacturing a flash memory device usually includes forming a device isolation film and then forming a polysilicon layer for a floating gate. The floating gate is formed by first etching the polysilicon layer for the floating gate, defining a gate electrode and then performing a self-aligned etch (SAE) process to form the polysilicon layer for the floating gate below a gate electrode. Recently, a method of forming the floating gate using a stepper mode and a method of forming the floating gate using a self-aligned floating gate mode have been widely employed in order to secure a space of the polysilicon layer for the floating gate.
The method using the stepper mode is one by which the polysilicon layer for the floating gate is deposited and a space is then defined through a mask process, wherein the polysilicon layer for the floating gate is defined as a bar type. At this time, the most import factor lies in how the space between neighboring polysilicon layers for the floating gates are defined to be narrow. This method has an advantage that the space between the polysilicon layers for the floating gates can be surely defined. This method, however, requires the mask process. Further, this method requires an expensive stepper as the design rule is reduced. Due to this, there is a problem that the cost of the flash memory device is increased.
Meanwhile, the method using the self-aligned floating gate mode is one by which the polysilicon layer for the floating gate is defined by a wet dip and poly chemical mechanical polishing (CMP) process without using the mask process. This method has an advantage that it does not require the stepper since the mask process is not performed. In this method, however, variation in the space may be hard depending on the wet dip time. Further, the process cost is increased since a poly CMP process is required. In addition, as an overlay between the polysilicon layer for the floating gate and a field oxide (FOX) film is determined by the wet dip, a hard moat is generated. A portion where the moat is generated, into which a channel ion is not injected, adversely affects an operation of a subsequent flash memory device.
In particular, in the method using the self-aligned floating gate mode, an erase operation of the flash memory device is problematic due to generation of the moat. If the coupling ratio is reduced, more higher bias is required upon a 0 erase operation. This increases the size of the capacitor in the flash memory device, thus causing the chip size to increase. In this connection, when all the flash memory devices are designed, it is important to secure the coupling ratio by maximum.
At this time, the capacitor of the flash memory device includes a capacitor (Cg) between the floating gate and the control gate, an overlay capacitor (Cd) between the floating gate and the drain junction region, an overlay capacitor (Cs) between the floating gate and the source junction region, a FOX capacitor (Cb) between the floating gate and the semiconductor substrate, and a free charge capacitor (Cf). The total capacitor (Ct) of the above capacitors can be expressed as the following mathematical equation 1.
Ct=Cg+Cd+Cs+Cb+Ctxe2x80x83xe2x80x83[Equation 1]
Further, the gate-coupling ratio (kg) can be expressed as the following equation 2.
kg=Cg/Ctxe2x80x83xe2x80x83[Equation 2]
The reason why the gate-coupling ratio is important upon the erase operation, is that the voltage (Vg) applied to the control gate is expressed as the floating gate voltage (Vfg) defined as the following equation 3.
Vfg=kgxc3x97Vgxe2x80x83xe2x80x83[Equation 3]
F-N (Fowler-Nordheim) tunneling is determined by the difference in the voltage between the control gate and the semiconductor substrate. Actually, F-N tunneling depends on a bias applied to the floating gate. Further, factors affecting the gate-coupling ratio include the thickness of the dielectric film having an oxide/nitride/oxide (ONO) structure and the area of the dielectric film surrounding the semiconductor substrate and the floating gate. The capacitor of the dielectric film is very important compared to other capacitors.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of forming a floating gate in a flash memory device, capable of reducing the cost with no use of a mask process compared to an existing stepper method and reducing the process cost with no use of a planarization process using a chemical mechanical polishing process (CMP) compared to a self-aligned floating mode, in such a way that upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird""s beak is formed on an internal surface of a trench by means of subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed.
In order to accomplish the above object, a method of forming a floating gate in a flash memory device according to the present invention, is characterized in that it comprises the steps of forming a tunnel oxide film on a semiconductor substrate; forming a lower polysilicon layer on the tunnel oxide film; forming a pad oxide film and a pad nitride film on lower polysilicon layer; forming a trench on the semiconductor substrate; forming an oxide film on the entire structure to bury the trench and then performing a planarization process; performing a first etch process to remove the pad nitride film and the pad oxide film and simultaneously to over-etch the oxide film; and forming an upper polysilicon layer on the entire structure and performing a second etch process to form a floating gate.